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| www..com JMB368 JMB368 PCI Express to PATA Host Controller Overview JMB368 is a single chip, 1-lane PCI Express to 1-port PATA Host Controller. It is designed to provide better PATA extension and compatibility, especially for chipsets without PATA. For these chipsets with only one PATA interface, JMB368 also provides a feature-up for Legacy IDE device supporting. It features PCI Express bus interface to lower pin count as possible. JMB368 supports PCI Express trace length can be up to 12" (30.48cm). Although the maximum length is up to 12 inch, the trace length is as short as possible on real application. JMB368 supports PATA trace can be up to 10" (25.4cm). Although the maximum length is up to 10 inch, the trace length is as short as possible on real application. PATA of JMB368 supports up to UDMA6. Serial damping resistors are necessary to keep UDMA performance. Please reference JMB368 Application Schematic in detail. Also, place these serial resistors within 0.5 inch of Host IDE Connector sid Feature Compliance * Compliant with Bus Master Programming interface for IDE ATA Controllers Revision 1.0 * Compliant with PCI Express Base Spec. Revision 1.0a * Compliant with PCI IDE Controller Spec. Revision 1.0 * Compliant with SFF-8038i Bus Master Programming Interface Revision 1.0 Overall * Integrated 1-Lane PCI Express PHY * Output swing control and Automatic impedance calibration for PCI Express PHY * Fabricated 0.18um/3.3V UMC CMOS Standard Logic Process with 2.0V and 3.3V * Available in 48-pin LQFP package * Co-layout with JMB361 and JMB363 PCI Express * Supports 1-Lane 2.5Gbps PCI Express bus * All registers accessible in unified memory space * PCI Express PCB trace length can be up to 8" (20.3cm) Copyright (c) 2006 JMicron Technology Corp. All rights reserved. Product Brief Reversion 1.1 Page 1 NDA Required 2006/10/12 www..com JMB368 PATA * Supports up to UDMA6 transfer mode of PATA * Supports up to 2 storage device connection * PATA PCB trace length can be up to 10" (25.4cm) Functional Block Diagram JMB368 62.5Mhz 100Mhz TX FIFO PATA NDA Required 2006/10/12 PATA Channel PCIE PHY MAC Layer Data Link Layer Packet & Flow Control PCIE I/F FIFO Packet Processing RX FIFO Diff. clock Target Cycle Block (Configuration Space & Register) Functional Block Diagram of JMB368 Copyright (c) 2006 JMicron Technology Corp. All rights reserved. Product Brief Reversion 1.1 Page 2 www..com JMB368 Product Information Name JMB368 Description PCI Express to PATA Host Controller Document 1 JMB368 Data Sheet 2 JMB368 Design Specification 3 JMB368 Hardware Design Guide 4 JMB368 Hardware Schematic Contact Information Department Sales Tech. Support Email sales@jmicron.com fae@jmicron.com Copyright (c) 2006 JMicron Technology Corp. All rights reserved. Product Brief Reversion 1.1 Page 3 NDA Required 2006/10/12 |
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